Signaling by FGF4 and FGF8 is required for axial elongation of the mouse embryo

AbstractFibroblast growth factor (FGF) signaling has been shown to play critical roles in vertebrate segmentation and elongation of the embryonic axis. Neither the exact roles of FGF signaling, nor the identity of the FGF ligands involved in these processes, has been conclusively determined. Fgf8 is required for cell migration away from the primitive streak when gastrulation initiates, but previous studies have shown that drastically reducing the level of FGF8 later in gastrulation has no apparent effect on somitogenesis or elongation of the embryo. In this study, we demonstrate that loss of both Fgf8 and Fgf4 expression during late gastrulation resulted in a dramatic skeletal phenotype. Thoracic vertebrae and ribs had abnormal morphology, lumbar and sacral vertebrae were malformed or completely absent, and no tail vertebrae were present. The expression of Wnt3a in the tail and the amount of nascent mesoderm expressing Brachyury were both severely reduced. Expression of genes in the NOTCH signaling pathway involved in segmentation was significantly affected, and somite formation ceased after the production of about 15–20 somites. Defects seen in the mutants appear to result from a failure to produce sufficient paraxial mesoderm, rather than a failure of mesoderm precursors to migrate away from the primitive streak. Although the epiblast prematurely decreases in size, we did not detect evidence of a change in the proliferation rate of cells in the tail region or excessive apoptosis of epiblast or mesoderm cells. We propose that FGF4 and FGF8 are required to maintain a population of progenitor cells in the epiblast that generates mesoderm and contributes to the stem cell population that is incorporated in the tailbud and required for axial elongation of the mouse embryo after gastrulation

IC3-Guided Abstraction

Abstract-Localization is a powerful automated abstraction-refinement technique to reduce the complexity of property checking. This process is often guided by SATbased bounded model checking, using counterexamples obtained on the abstract model, proofs obtained on the original model, or a combination of both to select irrelevant logic. In this paper, we propose the use of bounded invariants obtained during an incomplete IC3 run to derive higher-quality abstractions for complex problems. Experiments confirm that this approach yields significantly smaller abstractions in many cases, and that the resulting abstract models are often easier to verify

Sequential redundancy identification using transformation-based verification

textThe design of complex digital hardware is challenging and error-prone. With short design cycles and increasing complexity of designs, functional verification has become the most expensive and time-consuming aspect of the digital design process. Sequential equivalence checking (SEC) has been proposed as a verification framework to perform a true sequential check of input/output equivalence between two designs. SEC provides several benefits that can enable a faster and more efficient way to design and verify large and complex digital hardware. It can be used to prove that micro-architectural optimizations needed for design closure preserve design functionality, and thus avoid the costly and incomplete functional verification regression traditionally used for such purposes. Moreover, SEC can be used to validate sequential synthesis transformations and thereby enable design and verification at a higher-level of abstraction. Use of sequential synthesis leads to shorter design cycles and can result in a significant improvement in design quality. In this dissertation, we study the problem of sequential redundancy identification to enable robust sequential equivalence checking solutions. In particular, we focus on the use of a transformation-based verification framework to synergistically leverage various transformations to simplify and decompose large problems which arise during sequential redundancy identification to enable an efficient and highly scalable SEC solution. We make five main contributions in this dissertation. First, we introduce a novel sequential redundancy identification framework that dramatically increases the scalability of SEC. Second, we propose the use of a flexible and synergistic set of transformation and verification algorithms for sequential redundancy identification. This more general approach enables greater speed and scalability and identifies a significantly greater degree of redundancy than previous approaches. Third, we introduce the theory and practice of transformation-based verification in the presence of constraints. Constraints are pervasively used in verification testbenches to specify environmental assumptions to prevent illegal input scenarios. Fourth, we develop the theoretical framework with corresponding efficient implementation for optimal sequential redundancy identification in the presence of constraints. Fifth, we address the scalability of transformation-based verification by proposing two new structural abstraction techniques. We also study the synergies between various transformation algorithms and propose new strategies for using these transformations to enable scalable sequential redundancy identification.Electrical and Computer Engineerin

Scalable Liveness Checking via Property-Preserving Transformations

The ability of logic transformations to enhance safety property checking has been well-established, and many industrial-strength verification solutions accordingly rely upon a variety of synthesis and abstraction techniques for speed and scalability. However, little prior work has addressed the applicability of such transformations in the domain of liveness checking. In this paper, we provide the theoretical foundation to enable the efficient use of a variety of (possibly customized) transformations in a livenesschecking framework. We demonstrate the practical utility of this theory on a variety of complex verification problems.

Coping with Moore’s law (and more): Supporting arrays in state-of-the-art model checkers

Abstract-State-of-the-art hardware model checkers and equivalence checkers rely upon a diversity of synergistic algorithms to achieve adequate scalability and automation. While higher-level decision procedures have enhanced capacity for problems of amenable syntax, little prior work has addressed (1) the generalization of many critical synergistic algorithms beyond bit-blasted representations, nor (2) the issue of bridging higherlevel techniques to problems of complex circuit-accurate syntax. In this paper, we extend a variety of bit-level algorithms to designs with memory arrays, and introduce techniques to rewrite arrays from circuit-accurate to verification-amenable behavioral syntax. These extensions have numerous motivations, from scaling formal methods to verify ever-growing design components, to enabling hardware model checkers to reason about software-like systems, to allowing state-of-the-art model checkers to support temporallyconsistent function-and predicate-abstraction